Active work, in the lab.

A ternary vector database. Sharding broke the LSH candidate-recall ceiling and took held-out recall from 92% to 100%.

Ternary lookup-table compression for language models. On LFM2.5-350M it shrinks the model 3× and runs faster, with identical output.

A ternary soft-silicon operating system for ESP32-C6 (RISC-V) and ESP32 (Xtensa). It is the adaptive layer, built to run alongside Flynn's deterministic core across a clean certification boundary.

Signature Search & Ternary Topology: a zero-parameter image classifier that runs on integer table lookups small enough to fit in L2 cache.

Natural-language control for ESP32-class hardware, using twin-ternary nearest-neighbour routing over a small intent set.

A ternary routing transformer that behaves as a discrete program selector. Ternary routing outperformed binary routing and dense baselines, and stayed robust under data saturation.

A neural network that implements a 6502 CPU exactly, verified across every tested input combination.

The same 6502, rebuilt from splines at full accuracy.

Deterministic message-passing coordination between processes.

A vector database designed to live entirely in CPU cache, built on MTFP7, a custom 7-trit floating-point format.

An ARM NEON-optimised inference runtime for Raspberry Pi 4–class hardware.

A DNS for hardware components: hierarchical name resolution over a chip's memory-mapped I/O surface.

A bare-metal C99 substrate for ESP32-S3-class boards.

Unified Spline-LUT Architecture: models constructed directly from LCVDB topology, with spline control points as the trainable surface. Paused while other streams take priority.